RISC-V is an instruction set architecture (ISA) released by UC Berkeley. Besides, a high performance, power efficient, and royalty-free open source implementation Rocket Chip is available.

RISC-V was developed by Krste Asanović and David A. Patterson. In their technical report, they claimed that an open instruction set can benefit both academic and industry. They gave three arguments:

1. Greater innovation -- If there is an open instruction set and open implementations, we could have greater innovation since the developers or researchers can change the ISA, evaluate their new deisgn, and compare their design with the others. This is not possible with current proprietary ISA licensing models. Since most of the licensing models disallow the change of ISA. Some licensing model even prohibits the change of the ISA implementations.
2. Open development -- If the instruction set and its implementation is developed in open, more developers can read and audit the source code and find the possible errors. It is well-known that the open model works for operating system and compiler toolchain. And RISC-V is the one to fill in the missing piece for microprocessors.
3. Reduce cost -- If the ecosystem becomes mature, the price of the baseline chip will become as low as the manufacture cost since everyone can download the reference implementation and ask the IC foundries to produce the chip.

The design of the instruction set is yet anther question. The choice of the instruction is important since the ISA will last for several decades. A good design should include the essential features and exclude the unnecessary features. For example, it is necessary to have load/store instructions for byte, short, float, and double; but it is unnecessary to include delay slot and register window.

Krste and David predict that there are three trends for the computer evolution: IoT devices, personal mobile devices, and warehouse-scale computers. Thus, RISC-V follows these design concepts:

1. Base plus extension ISA -- More applications are accelerating the computation with ASIC, thus we have to leave the space for further extension of the core instruction set. This implies that we should leave sufficient encoding space for extensions. As a result, RISC-V has a core instruction set with several extensions. The bit operations, SIMD instructions, and compact instructions are defined as the optional extensions.
2. Compact instruction set encoding -- On the memory limited IoT devices, the code size will be an issue. It will be helpful to have compact instruction set encoding. There is a compact instruction extension which encodes the popular instructions in 16-bit (instead of 32-bit). This is similar to the Thumb instruction set for ARM, which has been proved to be useful to reduce the code size.
3. Quadruple-precision floating point arithmetic -- There are several WSC applications using quadruple-precision arithmetic to process a lot of data nowadays. It will be a good idea to include them to the instruction set.
4. Support 32-bit, 64-bit and even 128-bit address space -- The 32-bit address space is still important to the IoT devices due to their limited memory. However, 64-bit address make more sense for the other applications. Although there is no 128-bit usage at the moment, we have to leave sufficient room for extension. If we don't plan for larger address space in the early stage, it may be difficult to workaround in the future.

We can compare RISC-V with OpenRISC. OpenRISC is an open source ISA as well. However, due to the encoding of the immediate value, there is little encoding space left for extension. Besides, it lacks for compact instruction encoding and quadrupe-precision arithmetics. Furthermore, when RISC-V was developed, OpenRISC does not have 64-bit address space support at the time (although OpenRISC have 64-bit support now.)

In conclusion, RISC-V is an open source ISA which work hard to fulfill the design goals mentioned above. Besides, we can download the compiler and simulator right now. A non-profit organization lowRISC is developing the development board for RISC-V. I am looking forward to the future of RISC-V.